Dc-to-dc converter

ABSTRACT

A DC to DC converter embodying transistors in compound-connected multiple arrays, providing high current gain with special means for reducing switching losses, the arrays being driven in an alternate switching action to apply power pulses to an time-delay transformer under control of pulse-forming and gating subcircuits utilizing multivibrator means controlled by an inverter to produce sets of voltage-conformed gating pulses in such a manner that the power pulses are thereby shaped for substantially constant energy content as the result of automatically adjusting the duration of the pulses in inverse proportion to the instantaneous voltage of the DC source to produce a substantially constant output voltage between predetermined limits of source voltage for a given load condition. A low-loss reflex outputvoltage regulating means may additionally modify the pulse shape in response to load variations. A dual-function isolation and time-delay input circuit prevents feedback into the source and also cooperates with start-stop protective means to guard the power transistors against destructive current surges during turnon and turnoff of the converter.

United States Patent Primary Examiner-William M. Shoop, Jr.Attorney-Stone, Zummer & Aubel ABSTRACT: A DC to DC converter embodyingtransistors in compound-connected multiple arrays, providing highcurrent gain with special means for reducing switching losses, thearrays being driven in an alternate switching action to apply powerpulses to'an time-delay transformer under control of pulse-forming andgating subcircuits utilizing multivibrator means controlled by aninverter to produce sets of voltageconformed gating pulses in such amanner that the power pulses are thereby shaped for substantiallyconstant energy content as the result of automatically adjusting theduration of the pulses in inverse proportion to the instantaneousvoltage of the DC source to produce a substantially constant outputvoltage between predetermined limits of source voltage for a given loadcondition. A low-loss reflex output-voltage regulating means mayadditionally modify the pulse shape in response to load variations. Adual-function isolation and time-delay input circuit prevents feedbackinto the source and also cooperates with start-stop protective means toguard the power transistors against destructive current surges duringturn-on and turnoff of the converter.

(osc) [72] Inventor Robert W. Beckwith 1002 Greenfield Lane, MountProspect, 11]. 60056 [21] Appl. No. 812,104 [22] Filed Apr. 1, 1969 [45]Patented Aug. 24, 1971 [54] DC-TO-DC CONVERTER 9 Claims, 8 Drawing Figs.

[52] U.S.Cl 321/2, 321/l8,321/45R [51] Int. Cl H02m 3/22 [50] FieldofSearch 321/2, 18, 45

[56] References Cited UN lTED STATES PATENTS 2,663,806 12/1953Darlington 307/315 3,315,146 4/1967 Paice 321/45 2,341,765 9/1967Rogers, Jr. et al 321/2 3,373,334 v3/1968 Geisz et a1. 321/2 3,418,55712/1968 Schaefer 321/18 3,432,737 3/1969 Hunter etaL. 321/2 3,439,2514/1969 Schaefer 321/2 X FZIP INVERTER 530$ FLOP OUTPUT C K77 NETWK-OUTPUT.

NE/ms DC-TO-DC CONVERTER PRIOR ART Attention is called to US Pat. No.3,075,136 to Jones (CL. 321/45 as the closest art presently known; theconverter system therein disclosed employing different circuit means andcomponents from those disclosed herein and operating upon differentprinciples, including, among others, a control of pulse width byfeedback from an output circuit.

This invention has as its object the provision of a DC to DC convertersystem of a type utilizing solid state electron valve and switchingdevices and capable of providing a DC current of substantial magnitudeat a desired voltage from a DC source of different voltage.

While adapted .to general usage, the disclosed converter system isespecially advantageous in providing'a highly regulated DC supply at oneof the standard voltages (for example, 48 volts) presently used fortelemetering purposes, microwave and carrier communication and likeapplications at utilities power stations and substations having a localdirect current battery of a different voltage (for example, 125 volts)or a source which varies objectionably in potential due to loading byother equipment, maintenance problems or like causes.

The system described and claimed hereinafter is characterized by highefficiency, stability and compactness with complete feedback isolationfrom the station or source battery, optional grounded or nongroundedoperation, and excellent regulation in respect to variations in bothinput voltage and output loading, all afforded by novel circuit meanscomprising a combination of coacting subcircuits including an invertercircuit producing timing pulses at a substantially constant frequency; anovel power-switching transistor configuration for intermittentlyapplying power from the local DC supply in equal energy pulses to aspecial transformer forming part of an integrating output circuit; agating circuit controlled by said timing pulses and governing a drivermeans for the power-switching circuit in conjunction with a pulse widthcontrol circuit operative to modify the power pulses in inverseproportion to the voltage existing at the supply source, as well as inrelation to load variation at the inverter output.

A preferred illustrative embodiment of the invention in accordance with.the appended claims is described in view of the accompanying drawingsin which:

FIG. 1 is a block diagram depicting the relationship of the combinationof subcircuits comprising the converting system;

FIG. 2 is a detailed schematic of the input circuit means;

FIG. 3 is a detailed schematic of the output circuit;

FIG. '4 is a schematic of a pulse shaping and gating control circuitcooperative with the input and output circuits of FIGS. 2 and 3;

FIGS. 4, 6, 7, and 8 illustrate progressively expanded variations of thespecial power-switching transistor configurations.

In its general aspects, the converter system embodies the combination ofsubcircuits depicted by block diagram in FIG. 1 wherein the inputcircuit -A- constitutes an intermediate source of constantdirect-current taken for conversion from input terminals adapted forconnection with the local battery or DC supply (for example, but not bylimitation, a standard 125 -volt battery system at a power plant).

One of the functions of the input circuit is that of isolating theconverter by a series choke means from the local supply and otherequipment served thereby to prevent possible reflective disturbancescaused by substantial pulse voltages generated at the 800 and 1600 Hz.frequencies present in other subcircuits of the system, the output ofwhich is similarly isolated in respects pointed out hereafter.

Additionally, the input circuit provides an optional neutral groundconnection -Gr-; and an intermediate constant current supply sump inthey form of a parallel capacitance of sufficiently high value,cooperatively with the aforesaid choke means, to render the converterlargely independent of voltage fluctuations and other transientdisturbances in the local DC supply.

As indicated by the connecting lines A-l, A-2 and A-3 in FIG. 1, currentfrom the sump source is'gated in formed pulses alternatively to twowindings forming part of the split-winding primary of a specialtransformer T-l in the output circuit F, the respective energizingcircuits for each such winding being identical and completed in pulsedalternation under control of an intervening control circuit meanscomprising the inverter B, a gating control C, a gated power switchingmeans D, cooperative with a pulse width control E, and output regulationmeans G. I

The input circuit A, as seen in its more detailed aspect in FIG. 2, maybe connected with the local 125-volt battery or other DC supply atterminal 10 and 11 and, where required, to a working ground at terminalGr, it being noted that system ground connections are commonly avoidedin utility power installations by reason of their being a hindrance tofault location tests, and accordingly the converter ground Gr is madeneutral with respect to the local-battery by blocking diodes l3 and 14shunted by a capacitor 15 to bypass signalling frequencies formicrowave, carrier communication and like equipment served by theconverter.

An isolation choke 16 in an upper branch 38B of the DC current gated tothe power transformer, inhibits feedback of high-voltage pulses from thepower section and also effects uniform charging of a sump capacitor 17having a capacity of the order of 820 mfd. these components alsofunctioning in another mode as part of a start-stop time delay means.

DC current from the sump capacitor 17 is applied to a specialtransformer in the output circuit F in the form of gated pulses shapedand timed by the control circuit of FIG. 4 in a manner to be explainedin detail hereafter, such pulses being applied at terminals 20, 21 and22 of the split winding 23 of said transformer, which may have one ormore split secondary windings 24 and 24A. The center-tap terminal 20 ofthe primary winding connects via conductor 20A with positive potentialon the upper input feed bus 388 (FIGS. 2 and 4), and the remainingprimary terminals 21 and 22 respectively connect via conductors 21A and22A with corresponding gating terminals 216, 226 at the control circuitoutput, as will appear more fully hereafter.

Paired power pulses of square waveform and effectively identical energycontent are supplied in alternation to said transformer primary windingsand returned to zero to energize the same oppositely to avoid sustainedunidirectional flux components and to produce corresponding pulses inthe secondary winding 24 for rectification by diodes 25, 26.

The high degree of voltage regulation attained by the system is achievedin part by maintaining a constant ratio of width of the shaped powerpulses to the magnitude of the voltage of the local DC source and theload, together with integration of the rectified output currents into anaveraged current free of voltage spikes as the result of terminating therectifiers in a network presenting an input substantially free ofcapacitance and of predominantly inductive character.

Thus, the terminal network detailed in FIG. 3 presents an inductiveinput in the form of a choke 27 in series with the output of therectifying diodes 25, 26, a filter capacitor 28 being shunted across theoutput following this choke. Ripple filtering means follows the inputchoke and may take the form of a second choke 33 in series with choke 27and followed in turn by another shunt capacitance 31 across the outputto terminals 33 and 34, a Zener diode 33 being shunted across saidterminals for protective purposes.

Regulation in respect to fluctuations in the supply voltage, which inmost 125-volt installations of the type described can be expected tovary between 105 and 156 volts, is such as to hold the converter voltagebetween +7. and +2. volts of its 48-volt rating with an efficiency of topercent depending upon variations in supply voltage, and loadfluctuations rangfrom conditions inherent in the use of symmetricalcircuits to drive the transformer primaries in the manner shown; andminimization of iron losses in the transformer caused by the range offrequency attending use of the square wave configuration.

The transformer losses are substantially alleviated by employment of atoroidal construction for the output transformer T-] with ahigh-efficiency nickel-iron core and bifilar windings in both primaryand secondary operative to reduce transient effects and designed tooperate at about one-third the ampere turns which would producesaturation.

The efficiency of the system is still further improved by use of aferrite core in choke 27 in the output network to reduce lossesotherwise resulting from the high square wave voltages developed acrossthe respective windings thereof.

A further regulation, effected as a function of load variation, involvesa reflex circuit which is isolated from the metallic circuit of thecontrol circuit means of FIG. 4 by use of photore'sistive means, as willappear in the description to follow.

Means for converting DC source current to voltage-conformed constantenergy pulses energizing the primary windings of the output transformer,in alternation, as described in view of FIG. 3, comprises thecombination of subcircuits heretofore generally designated in the blockdiagram of FIG. 1, as the inverter B, gating control C, gated switchingmeans D, pulse width control E, and reflex load regulation means G, allutilizing solid state electron control devices to produce, in timedsequence from the local DC supply, pairs of square wave,width-to-voltage proportioned power pulses such that the pulses of eachpair are substantially identical in shape and energy content andproportioned at least to the input supply voltage, and adapted to beintegrated as an averaged output current at substantially constantvoltage by the output circuit means.

The inverting means is the source of primary control pulses and, as seenin FIG. 4, may comprise a simple relaxation oscillator preferablyutilizing a unijunction transistor Q-l, having first and second baseelectrodes 41, 42 respectively connecting to bias voltage throughresistors 44 and 45 from positive and negative feed conductors 38A and39A branching from the DC input terminals and 11, the unijunctionemitter 43 being pulsed from an RC timing means consisting of resistor47 in series with a'capacitance 48 across said feed conductors andhaving a time constant operative to fire said transistor at a preferredfrequency of 1600 cycles per second and provide two timing pulses ineach cycle, to drive the flip-flop at 800 Hz,

The voltage on the feed conductor 38A and its branches is regulated by aZener diode 40 shunted thereacross through resistor 40A. The oscillationperiod of the unijunction inverting means will be substantially constantat the required frequency, subject only to inconsequential variation dueto component characteristics.

Alternate gating pulses for the two side circuits of the power switchingmeans are provided by multivibrator means including a bistable flip-floptype employing transistors Q-5 and Q-6 connected in the network shownfor mutually cross-controlling firing and extinction responsive totrigger pulses supplied by the unijunction oscillator via conductor 42Afrom the,

base-2 unijunction terminal and applied to the signal side of twocoupling capacitors 52 and 53 each of which will supply, via respectiveconductors 52A and 53Aand corresponding series resistors 52B and 533, atrigger pulse operative at the appropriate time to turn on theappertaining transistor which happens to be off, and turn off thetransistor which is conducting, in the known manner, such that the twotransistors are.

toggled in alternation from ON to OFF conditions to produce two gatingpulses per cycle of the oscillator, whereby the output transformer willbe pulsed at a frequency of 800 Hz. by precisely equal pulses appearingat the respective collectors 55, 56 of transistors 0-5 and 0-6 andapplied via respective collector leads 55A and 56A to corresponding gatediodes 57A and 58A, each of which constitutes one ofa pair of gatediodes 57A--57B or 58A58B, the said diode pairs respectively comprisingfirst and second pulse gates for the two transformer primary windings.

Thus, the first pair of gate diodes 57A-57B controls appli cation ofenergizing power pulses to primary winding 20-21, while the secondpairof diodes 58A58B controls the pulses to winding 20-22. I V

The pulse gates are enabled or opened" when the voltages on bothcathodes of either pair of diodes go to zero simultaneously; but thiscondition can exist in the configuration shown only when the flip-flopcauses one diode of a given pair to go to zero, and the pulse-stretchingmeans likewise causes the voltage on the remaining diode of the saidgiven pair to go to zero at the same time. Under the conditionsdescribed, these gates may be considered as AND gates for zeros.

Thus, the alternate determinant signal conditions from the flip-flopsubcircuit can enable the corresponding gates only with the concurringdeterminant signal conditions from the output of the pulse-stretchingmeans both caused to occur at some particular angular position in eachhalf-cycle of flip-flop operation, the said angular position alwaysbeing a function of the instantaneous voltage afforded by, or existingat,-the local or primary DC supply terminal 10 and 11.

Regarded in another way, there will be a particular instant in eachhalf-cycle of the gating operation during which the pulse-stretchingmeans will provide the necessary zero-potential condition for one of thegate diodes of a given pair at the same instant the companion diode ofsuch pair is also brought by the pulse stretching means to theconcomitant zero-potential condition necessary to satisfy the gate open"requirements; and the particularly instant in each half-cycle when theoutput potential thus controlled by the pulse-stretcher fulfills thiszero-voltage condition is determined by the voltage existing at thatinstant at the supply battery, that is to say, from moment to momentthereat.

The aforesaid positioning of the gating pulse in each halfcycle isachieved by use of an RC timing means in the pulse stretcher unit toproduce a firing potential in a capacitor the charging rate for which isdetermined by an associated resistance in series with the chargingvoltage (effectively the local input voltage) whereby the charging timewill vary inversely with the voltage ofthe supply, and hence theparticular instant when the charge reaches firing potential willdetermine at what instant, early or late in each half-cycle when thepower pulse will be gated to the transformer, which in turn is istantamount to determining the width (full or less than full), andtherefore the energy content, of the power pulse.

Thus, if the supply voltage is high, the RC control potential in thepulse-stretching subcircuit is reached early inthe square wavepower-pulse interval, causing the output of the pulse stretcher to'go tozero sooner, with a shorter pulse duration than will be the case whenthe supply voltage is lower and the RC control potential requires alonger time to reach the control potential and therefore permits thepower pulse to persist longer. The circuit parameters are chosen so thatthe gating pulses at the maximum expected local supply or batteryvoltage (commonly 156 volts in the usual l25-volt system) are completedin less than the full half-cycle allowed for each pulse ofa pair.

The circuit means E which monitors and regulates the inverter outputvoltage by pulse width adjustment, as aforesaid, comprises transistors0-2, 0-3 and Q-4 connected in the monostable configuration shown in FIG.4 for bias from the branch feed conductors 38AA and 39, the operationbeing such that a positive triggering pulse taken from base-1 of theunijunction transistor 0-1 in each firing thereof is applied viaconductor 41A to the base 50 of Q-2 causing the latter to conduct andinstantly discharge capacitor 60 thereby turning off transistor 0-3 andturning on 0-4 to reduce the voltage on conductor 61 and gate diodes 57Band 588 to Zero during an interval when one or the other of the gatediodes 57A or 58A will be in the zero potential condition required togate a power pulse to the output transformer through the specialtransistor switching means D as the result of firing one or the other ofthe driving transistors Q-7 or -8.

Thus, assuming that the gate diodes 57A58A of the upper pair are broughtto the zero-potential, or open-gating condition described, the potentialon base 62 of 0-7 causes conduction in the circuit through collector 63and emitter 64 thereof to provide a shunt path, via conductor 63A, Zenerdiode 65 and conductor 63B, to negative feed conductor 39A, thusremoving the turn-on bias for base '70 of transistor Q-9, therebyturning off the latter and its associated transistors Q- 10 and 0-1 1forming the special power array of the upper arm of the power-switchingsubcircuit, whereby to terminate the power pulse theretofore applied totransformer terminal 21 via conductor 21A and terminal 21G.

Exactly the same operations occur in the lower arm of the full-wavepower-switching circuit in respect to turning off the driver transistor0-8 and transistors Q-l2, Q13 and 0-14 to extinguish the power pulse tothe other half of the primary winding at terminal 21 via conductor 21Afrom transistor Q- 14 and output terminal 22G. Diodes 68 and 69 areprotective to block inverse voltages induced in the transformer windingsor across the input filter choke and are mainly precautionary in respectto these and possible switching transients.

The turn-on bias applied to base 70 of Q-9 is derived through resistor83, and that for the base 89 of 0-12 in the lower power arm is derivedthrough resistor 84, it being observed that the respective currentsthrough these resistors do not traverse the load and represent wastedpower, which constitutes one reason requiring the power gain of theswitching transistors to be quite high, other reasons includingswitching losses and unavoidable overall network losses. All such lossesand the high output of the system (e.g. l0 amperes at 48 volts for theconfiguration of FIG. 8) would require single transistors in each arm orside circuit of the full-wave output circuit to have a current gain ofabout 400; but transistors capable of such performance are notcommercially available, and for such purposes the novel configuration ofgrouped arrays of parallel transistors with a common driver, such asdisclosed in FIGS. 4 or 8, has been adopted with the object not only ofattaining these and greater current gains efficiently,

but also of combining thetransisto'rs' in a way such that the current ofthe initial transistor in each compound array will traverse the loadregardless of how many transistors comprise such array, as particularlybrought out in FIG. 7, for example; and further, to combine thetransistors in such a way as will eliminate balancing networks such ashave heretofore been commonly required in other multiple transistorarrangements having as their purpose an increase in current gain.

Transistors 0-9, 0-10 and -Q-1l, comprising the powerswitching tripletin the upper arm of the array of FIG. 4, are connected with theircollectors in parallel and their emitters effectively in parallel, andare driven in effect as a single transistor by a driver such as 0-7.Thus, all of the appertaining collectors 71, 74 and 77 of the driventrio are tied together; and the emitter 72 of 0-9 is connected to thebase 73 of the succeeding transistor Q-IO whose emitter 75 connects inturn to the base 76 ot'the last transistor 0-] l, the emitter 78 of thelatter constituting one terminal ofan energizing circuit for one primarywinding of the output transformer which is completed via collector 77and terminal 21 of said winding when the array 0-9, 0-10 and 0-11 isconductive.

In every such power array, each emitter-to-base interconnection will betied to a joint or common emitter connection through acurrent-equalizing means such as the resistors 79 and 80; while anotherresistor 81 from the base 70 of the leading or input transistor 0-9 ofthis set accelerates turnoff by providing a path for escape of currentcarriers to negative bus conductor 38A. The base 70 of 0-9 is normallybiased for turn-on through resistor 83 from supply conductor 38, but isshunted for turnoff by the drop through the collector 63 and emitter 64of driver 0-7, as previously explained. A Zener diode 65 assurespositive turnoff and turn-on of 0-9 to guard against differences intransistors (such as 0-7) by fixing the turn-on voltage of 0-9 (e.g. atvolts) so that marginal voltage wont turn 0-9 on when it is supposed tobe off. 1

Since the power switching configuration is symmetrical for full-waveenergization of the transformer, the companion array or trio oftransistors in thelower arm or side circuit, comprising transistors0-12, 0-13 and 0-14, will be understood to consist of like componentsand to operate in exactly the same manner as the array in the upper armjust described.

The principle of operation of the foregoing power-switchingconfiguration is explained in view of the more simple array of FIG. 5,wherein the transistors Qa and Ob may be considered of equal rating, andresistor Ra provides a conductive path for elimination of chargecarriers from intermediate bases, such resistors desirably having avalue selected to equalize the current passed by Qa and Qb, in whichcase Ra will cause no additional loss, since the product of the totalcollector current and current in the case of a two-transistor 5, or toone-third in a triplet array according to FIG. 6, and so thecollector-emitter drop across Qb must be lost in any event.

Since the maximum voltage to appear across Rb in the example of FIG. 5will be the forward emitter-to-base voltage, a value of resistance forRb can be found which will not absorb any appreciable additional power,and this array can be treated as a single transistor wherein the totalcurrent gain will be very nearly equal to the sum of the individualcurrent gains of the two transistors of the set (neglecting Rb while thetotal collector current will be exactly the sum of the respectivecollector currents of the two or other number of transistors, it beingnoted, again, that the IR drop across the collectoremitter pathrepresents a form of loss in every case.

The explanation for the improved performance of these compound powerconfigurations is believed to be that the intertransistor bypassingpaths of predetermined conductivity or resistivity represented by theresistors Ra, Rb, Rc, etc., are responsible for an appreciable speedingup of the turnoff characteristics of the several transistors comprisingthe set, along with a 9 eduction in transient effects in the overallpower circuit, which action in turn is believed very probably due torapid elimination of charge carriers during turnoff.

The resultant single transistor behavior of the power arrays is suchthat arrangements like that of FIG. 5 can be expanded to include threetransistors in a tandem triplet configuration such as shown in FIG. 6,which may be regarded as the equivalent of the configuration of one ofthe primary side circuits of FIG. 4, with transistors Q-9, Q-l0 and 0-11of the latter corresponding to Qa, Oh and Q0 of FIG. 6. By way ofillustrating relative component values which might be used for theequalizing resistors in such an arrangement, it may be assumed that thethree transistors are types 2N 3902, and that the collector-emitter biasvoltage will be the full supply voltage (e.g. V.) on supply bus 38, andthat the load impedance is represented by the output circuit includingthe transformer and its terminating network and a load in the expectedrange, under such conditions, and assuming a desired output current offour amperes, equalizing resistors Ra and Rb could have a value of about1000 ohm each, while Rc could have a value of only 10 ohms it beingobserved that the base resistors, such as Ra in FIGS. 5 and 6,contribute to rapid turnon but do not participate in equalization ordistribution of the emitter currents as do resistors Rb and Re.

While the addition of equalizing and turnoff resistors such as Ra, Rb,Rc, etc. would appear to involve a disadvantage in that the individualcurrent gains are reduced by the equalization to that which might betheoretically obtainable at halfarray according to FIG.

on, actually it is found that an increased drive is achieved which isself-regulating and produces an unexpected improvement in the overallperformance of the set, regarded as a single transistor, owing to thefact (referring again to FIG. 5) that if Qb is caused to have lesscurrent gain than normal, and Qa is driven to saturation, then morecurrent will flow in Qa, and Qb will be driven harder and the net resultof the sum of these gains will represent an increase plus significantadvantages in faster turnoff time, lowered operating temperatures, andsome transient relief.

The significance of current equalization within an'array may beillustrated by assuming (again with reference to FIG. that if an overlyhigh resistance is substituted for Rb to begin with, some improvement inturnoff will nevertheless be observed; but if such resistance is thenprogressively lowered, more and more current is diverted from Qb until avalue of resistance will be reached at which the division of currentbetween thetwo transistors becomes about equal, and this condition willrepresent the optimum working value in which the total current gain,switching response and time will bea practical maximum.

Consistantly with the performance of arrays such as those of FIGS. 5 and6 as single transistors, it becomes possibleto further compound theconfigurations in sets of parallel arrays in the manner shown in FIG. 7wherein duplicate sets of twotransistor arrays, designated as Set I andSet II for reference, are connected with the respective bases B and B ofthe respective input transistors Qa and Qa in each set tied together asa single input base terminal b, while all of the collectors Ca, Cb, andCa Cb are tied together with a single collector terminal c, therespective emitters Ea, Eb and Ea, Eb likewise being joined with asingle emitter terminal e. Each of the sets I and II is provided with acorresponding complement of equalizing resistors Rb, Rb, but with onlyone turnoff resistor Ra.

FIG. 8 illustrates still another modified configuration asan I expansionof the arrangement of FIG. 7, and one which is shown in condition forsubstitution for the power transistor system of FIG. 4 to yield ahigh-current output of the order of 10 amperes at 48 volts, it beingobserved in FIG. 8 that each of the side circuits for the two primarywindings of the power transformer consists (referring to the upper arm)of two sets of arrays III and IV characterized in that set III employsthree transistors,while the companion parallel set IV employs only two,which is substantially a combination of FIGS. 5 and 6, or of FIG. 7wherein FIG. 5 (regarded as a single transistor) replaces Qb in set I.

Thus, the number of compounded transistors in each array, and themultiple combinations of various arrays in parallel connection, may beextensively varied to achieve increased current gain while preservingthe rapid-switching action and other benefits afforded by the equalizingresistors, it being observed that in all such compounded multiple arraysas exemplified by FIGS. 7 and 8, for example, the current gains forindividual arrays in what may be designated for reference as a tandemarrangement, will afford a total current gain which will be very nearlythe sum of the current gains of the individual transistors comprisingthe array, whether two, three, or more; and the total gain for theentire configuration will be the sum of the current gains of all of thearrays which are connected in parallel, ignoring the small turnoff andequalizing"losses.

Thus the current gain of the configuration of FIG. 5 is very nearly thesum of the individual gains of Qa and Qb; and that of FIG. 6 the sum ofthe current gains of Qa, Oh and Q0; while the gain for FIG. 7 is the sumof the current gains of Ga and Qb to which is added the sum of 0a by Ob;the gain for FIG. 8 being the sum of Qa, Qb and O0 to which is added thesum of Ga and Qb (neglecting as always nominal losses caused byinclusion of the turnoff and equalizing resistors Ra, Rb, Ra, etc.). Inall other respects the variously expanded compound configurations canall be treated as asingle power transistor driven by a single drivingtransistor and producing the increased current gains noted in eachinstance with. markedly decreased switching losses attended by loweroperating temperatures, the latter improvement being considered to bethe result of reduction of the switching time, for example, from 10 to lmicroseconds.

While such switching arrays can easily handle many amperes of current,they require protection from excessive voltage surges which can actacross the collector-emitter paths both when the system is first turnedon, and when it is shut-off. As will appear from a consideration of FIG.4, when the power is first switched on the full supply voltage at the DCsource (e.g. 105 to 156 v.) could act in the transistor power circuitsthrough the transformer primary windings if either array happened to bein the conductive state, since the output circuit which terminates thesecondary windings offers very low impedance at such times owing, amongother things, to'the discharged condition of capacitors 28 and 31. Undersuch conditions the possibility always existsfor either or both thiscircuitry being designated generally in'FIG. 1 as the Start-Stop GuardMeans"l-I and which comprises, with reference to FIG. 4, first, thecoaction of the inductance of the supply input choke 16 and thecapacitance of sump capacitor 17, functioning in another mode as atime-delay circuit affording several milliseconds lag in the rise of thesource voltage when the converter is first turned onj said guard meanscomprising, secondly, parts of the network within the dotted-lineenclosure of FIG. 4 acting during such turn-on delay interval toaccelerate the action of the pulse-stretching circuit by effecting amaximally rapid initial charging of the relatively much smallercapacitance 60 (approximately 0.01 mfd.) which formspart of the R/Ctiming means for the pulse stretcher, acting through the relatively muchgreater capacitance (about 1.0 mfd.) of a capacitor 91 which is chargeddirectly from raw DC source voltage on bus conductor 38 (bypassing chokel6 and capacitor 17), with the result in the pulse-stretcher thattransistor Q-3 is almost instantly turned on, and Q-4 accordingly almostinstantaneously turned off at the moment the converter apparatus isswitched on.

The latter turn-off of Q-4 causes a maximum momentary narrowing of thegating pulses on conductor'6l, while at the same moment thepower-switching begins by brute force action of raw source voltage'fromconductor 38A (i.e. bypassing choke 16 and capacitance 17) on theinverter transistor Q-l to start the toggling action of the flip-flopcircuit. Thus, at turnon the narrowing of the power pulses and startingof switching 7 section is caused to be substantially simultaneous.

In the aforesaid guarding network 90, the said larger capacitance 91 hasits series resistor 92 shunted by a diode 93 in series with a breakdowndiode 94 with the latter connected to shunt said capacitor 91, so thatthe latter will be rapidly discharged, during turn-off of the convertersystem, through said diode 93; but as soon as the system reaches asteady state following tum-on, the Zener diode 94 breaks down and thispart of the network 90 thereafter performs what is, in effect, anamplifying function because of its nonlinear operation in compensatingfor output whenever the input or source voltage decreases, in accordancewith the following explanation. I

When capacitor 91 is fully charged, the resultant voltage across diode94 causes the latter to conduct, and this amounts to a subtraction ofvoltage from the source across said capacitor 91. At the desired upperlimit of the source voltage (eg 156 v.) the pulse width determined bythe aforesaid combination of resistor 92, diode 94 and capacitor 60,will be narrowest, and a substantial part of the (excess) source voltagewill be dropped across the Zener diode 94; but as the source voltagedrops toward the lower limit (eg v.) the proportion of source voltageacting across the resistor 92 increases nonlinearly owing to a nonlinearchange in the drop across the Zener diode 94, and the pulse width widensaccordingly to maintain the output voltage substantially constant, itbeing for this reason that the controlling effect of this network isconsidered one of amplification in respectto its nonlinear fu'nction incontributing to the regulation of.the output voltage in relation tochanges in input or source voltage.

When the converter system is switched on, the 1.25-volt DC sourceconductor 38B connecting with the power transistors the previouslyexplained surge charging of the small timing capacitance 60 through themuch larger capacitance 91 in the guard circuit section 90; therelatively large turn-off-and holdover capacitance 95(10 mfd.) however,is prevented from charging rapidly because of the series resistance 97(about 47 k. ohms) with'the result that the pulse stretcher, like theflipflop, begins operations instantly at turn-on to start thepowerswitching action.

When the converter is switched out of service, capacitor 95 willdischarge through diode 96 to apply power tofeed conductors 38A and38AA, whereby to continue the switch action until sump capacitor 17 isfully discharged. Also, at turnoff, the capacitance 91 will bedischarged through diode 63.

The close voltage regulation of the system is further ex tended tocompensate for changes in output voltage caused by.

variations in the load, this part of the regulation being achievedby asubstantially lossless photoreflex pulse width control means generallyindicated in FIG. 4 at 100, and comprising aphotoresponsive resistance98 connected in series with limiting resistors 46, 99 across thesource-voltage feed conductors 38,'38C so as to be, in effect, inparallel with the pulse width control portion of the Start-Stop GuardNetwork 90, said photoresponsive resistance 98 being effective tomodifythe charging .rate of thetiming capacitor 60 of thepulse-stretcher independently of the R/C constant of capacitor 91 andresistor 92 therein.

The photosensitive resistor means 98 will preferably be of thecommercially available type having encased therewith a light source 101connecting via conductors 101A, 1018 across the output terminals 33, 34,as in FIG. 3, so that the light intensity will change in proportion totheoutput voltage, variable resistance means-1 02 being provided toadjust the response-for the desired output leveL'A protective Zenerdiode 103 is shunted across this light source'toconduct at an uppervoltage limit and prevent premature and accidental burnout of the lamp,there being a second Zener diode.l04' in se-,

101 increases thus increasing the conductivity of photoresistor 98 andtherefore the voltage on the timing capacitor 60,

'on. In the case of a DC-to-DC converter, such imbalance can beparticularly detrimental and cause severe overheating in one or theother banks of power transistors.

, Assuming, generally, that the power transformer is of suitable qualitytobegin with, a major portion of this trouble arises from unequaldriving of thetwo primary windings. Further aggravated by imbalanceeffects reflected from the secondary circuit including contributionsfrom the rectifying diodes. Some of this kind of imbalance can berelieved by careful choice of transistors, diodes, and associatedcomponents, and by adjusting the turns in the' twoprimaries; however,these are largely empirical expediencies having no predictable constancyand, when attempted, mainly add to manufacturing costs without assuranceof permanence.

transformer Ahighly satisfactory means for alleviating such imbalance isafforded'in the control circuitry of FIG. 4 by inclusion of drivebalancing or equalizing means serving to strengthen the weaker, andweaken the stronger of the two pulses of each -pair of power pulsesdelivered to the respective transformer primary windings, for; example,by shortening the stronger pulse and lengthening the weaker pulseautomatically. Such reciprocal pulse-balancing action is achieved by'selective connection of a small balancing capacitance between the col-.lector of one or the other of the flip-flop transistors 0-5 or Q- 6,'andthe collector of the pulse-stretching transistor Q-2, depending uponwhich of the power-switching transistor arrays is contributingprincipally to the imbalance, selector switch means 121 being. providedto connect this balancing capacitance to the appropriate flip-flopoutput, once the offending source is identified. I

The operation of the aforesaid imbalance-correcting means 120 is suchthat inone alternation there will be an increase in voltage at flip-flopterminal 122, followed by a decrease at terminal 123 in theotheralternation (or vice versa depending upon the position of switch 121)with the result that timing capacitor 60 will have its charge increasedin the first instance and decreased in the second, or vice versa, with aconsequent shortening or lengthening of the appertaining switchingpulses and a resultant balance or equalization in the energization ofthe two transformer primaries which tends to prevent overdriving in oneor the other phase of each alternation.

It can be shown that such overdriving occurs in aspiked current portionof the offending power pulse, which represents a powerless voltage risemost easily detected by use of an oscilloscope to display the spikes inthe power pulses either at the outputs of theswitching transistor arraysor in the types of load, it is desirable to include aspike suppressingmeans in the form seen in FIG. 4, consisting of a capacitor 125 (e.g.about 0.03 mfd.) and a series resistor 126 (e.g. about 5,000 ohms)shunted across the entire primary, it being noted that this type ofspike control is of a'different characterfrom that intended by 'themeans 120, 121 in respect'both to the magnitude and cause of thespikingl It is contemplated that the foregoing apparatus as specifi-.cally shown and described by way of example and explanation of apreferred e'mbodimentand mode' of operation-thereof, may be modifiedwithin the scope of the appended claims. The particular form of thepulse generating, timing, shaping, gating and switching arrangements maybe changed and, depending upon the service required, someof thesubcircuits and features of the describedsystem may be omittedoraltered, for example, the rectifying and pulse-integrating means of theoutput circuit may be omitted if it is desired to use the device as-aninverter; or the reflex voltage regulating means may be omitted from theoutput circuit where a fixed load is applied or the load causes onlyslight or noncritical voltage variation. The transistor means in theswitching circuit may be reduced to a single transistor or otherelectron valve device in each side circuit (in the case of full-waveoperation) or the simplest of the compound-transistor arrays, accordingto FIG. 5, may be employed where output currentrequirernents arerelatively moderate; and-if'highest eff ciency is not demanded, thewinding in the output transformer need not be of the bifilar characterdescribed, but may be of common commercial grade, and may comprise anautotransformer.

Iclaim:

l. A DC-to-DC converter comprising an input circuit adapted forconnection to a sourceof direct-current; an output circuitadapted todeliver DC to a load and including a linear transformer having a primarywinding and a secondary winding, ciintrol circuit means operative fromsource current to generate timed and shaped control pulses theamplitudes of which are substantially constant and the duration of whichare conformed in inverse magnitude to the instantaneous voltage of thesource; switching means actuated by said control pulses to apply sourcecurrent in successive power pulses to said primary winding whereby thelatter is energized by pulses of source current which have asubstantially constant energy content; means in said output circuitoperative to rectify and integrate power pulses derived from saidsecondary winding to provide a unidirectional and substantially steadystate current for utilization by a load, said transformer primarywinding being split into two sections and said switching means beingactuated in power cycles by gating pulses applied thereat in each powercycle, and said control circuit means includes an oscillator providingtwo timing pulses per cycle of oscillation, together with multivibratormeans triggered under control of both timing pulses in each oscillatorcycle to produce angularly spaced gating pulses in pairs in each powercycle with the spacing between the successive gating pulses in each pairbeing changed in inverse proportion to each change of source voltage atany given instant from said normal value thereof, said switching meansbeing operative under control of each pair of gating pulses in eachpower cycle to switch a power pulse of source current into a differentone of said primary 'sections, multiple arrays, each comprising aplurality of transistors having base, emitter and collector electrodes;said multiple arrays comprising a group operatively associated with eachtransformer primary section, and the several arrays comprising each saidgroup being connected in parallel and with the bases of the firsttransistor in each array of the group being connected to define a jointinput base terminal, driving circuits, said joint input base terminalconnecting with a corresponding driving circuit, and the respectivecommon collector terminals connected to define a joint collectorterminal; and the emitter electrodes of the last transistors in eacharray being connected to define a joint emitter terminal, and the saidjoint collector and emitter terminals being connected to source currentthrough the appertaining primary section.

2. Apparatus according to claim 1 wherein the windings comprising theprimary sections and the secondary of said transformer are of thebifilar type, and pulse-integrating means in the output circuit forpresenting a predominantly inductive input to the rectified power pulsesderived from the secondary winding as aforesaid.

3. Apparatus according to claim 2 further characterized by the provisionof means for adjusting for overdrive in one or the other of saidtransformer primary sections due to difference in strength between thepower pulses produced in companion half-cycles of any full power cycle,said adjusting means including means selectively connectable with saidcontrol circuit means to modify the respective control pulses duringeither half-cycle of any given power cycle, such that the weaker pulsesof one half-cycle is widened and the stronger pulse of the companionhalf-cycle is narrowed, each respectively by an amount proportioned withrespect to the other to produce substantially equal driving effects forthe appertaining power pulses respectively energizing said primarysections in the given power cycle.

4. Apparatus according to claim 1 further characterized by the provisiontherein of output voltage regulating means including a device responsiveto voltage in said output circuit and cooperative with said controlcircuit means responsive to changes in output voltage from apredetermined normal value thereof, to modify the duration of saidcontrol pulses in inverse magnitude to the voltage existing in saidoutput circuit from moment to moment, but substantially independently ofthe conforming action effected by said control circuit means responsiveto changes in source voltage, whereby to maintain said output voltagesubstantially at said normal value thereof.

5. Apparatus accordingto claim 1 further characterized by ing withsource current and said first subcircuit means for operation to delayaction of full source voltage when the converter circuit is turned onfor operation by said DC'source until'such time as said first subcircuitmeans is fully operative in switching action as aforesaid; saidstart-stop subcircuit means being further operative to supply power tocontinue said switching action apredetermined length of time after saidconverter circuit is turned off tostop operation thereof by said. DCsource. v

6. Apparatus according to claim 21 wherein the said conformation ofparameters is such as to reduce the energy content of saidpulsesto apredetermined low value during the start, at least, of said switchingaction.

7. A DC-to4DC converter including a power transformer having a secondarywinding delivering converted DC energy to an output circuit, and aprimary winding energized by power pulses of direct-current from a DCsource having a predetermined normal voltage; circuit means operative incycles at a predetermined frequency to convert source current intosquare-wave power pulses at said frequency; switching means operativeresponsive to gating pulses in sets including a first and a last gatingpulse in each set to apply said power pulses in power cycles to saidprimary winding; means generating gating pulses in sets as aforesaid andapplying same to said switching means in power cycles each including atleast one set of gating pulses; the angular spacing between the firstand last gating pulse of each said set determining the width of eachcorresponding power pulse; and pulse width control means operativeresponsive to the magnitude of the existing source voltage during anypower cycle to position the last gating pulse angularly relative to thefirst such pulse in each set initiating a power cycle to determine anormal pulse width corresponding to said normal source voltage, saidpulse width control means being further operative to change suchposition in an inverse proportion to the deviation of said sourcevoltage from said normal value from cycle tocycle and thereby adjust thepulse width as necessary from time to time to maintain a substantiallyconstant energy level in said power pulses notwithstanding variations insource voltage between predetermined limits, at least.

8: Apparatus according to claim 7 wherein said pulse generating meansincludes timing means employing resistance and capacitance in an R/Ctiming combination the timeconstant of which is variable in'accordancewith the magnitude of a charging voltage acting therethrough, and saidR/C combination is connected to be charged by the voltage of said sourcewhereby to alter the angular relation between the first and last pulsesof any set of gating pulses to determine said normal and adjusted widthsin the manner and for the purpose aforesaid.

9. In a DC-to-DC converter circuit adapted to be connected to a sourceof direct-current and turned on and off in respect thereto to start andstop the converting action thereof, the combination with an outputcircuit adapted to deliver converted DC to a load; transistor meansadapted to be turned on and off in switching action to energize saidoutput circuit in power pulse of DC conducted thereto by said transistormeans; timing circuit means operative to actuate the transistor means inswitching action as aforesaid; and start-stop guard means comprising afirst subcircuit means operative to prevent action of full sourcevoltage in said transistor means at starting turn on of the convertercircuit for a predetermined delay interval; means cooperative with saidtiming circuit means to cause said switching action to be in fullprogress during said interval; and circuit means operative to continuesaid switching action a predetermined time after the converter circuitis turned off to stop the converting action.

Patent No. 3,601680 Dated Angnfit 24 191] Inventor(s) Robert W. BeckwithIt is certified that error appears in the above-identified patent andthat said Letters Patent are hereby corrected as shown below:

Abstract, Line 5, "time-delay" should be -output-.

Column 1, Line53, "4" should be --5--. I

Column 2, Line 13, "terminal" should be terminals-.

Column 2, Line 27, after mfd." insert Column'4, Line 24, "terminal"should be -terminals.

Column 4, Line 32, "particularly" should be particular--.

Column 6, Line 37, "9 eduction" should be -reduction-.

Column 6, Line 58, after "ohms" insert Column 8, Line 23, after "H"insert Column 8, Line 50, "section" should be --action-.

Column 9, Line 67, Further" should be further.

Column ll, Line 53, "pulses" should be pulse--.

Column 12, Line 12, "21 should be 5-.

Signed and sealed this 18th day of April 1972.

(SEAL) Attest:

EDWARD M.FLETCHER,JR. ROBERT GOTTSCHALK Attesting Officer Commissionerof Patents J

1. A DC-to-DC converter comprising an input circuit adapted forconnection to a source of direct-current; an output circuit adapted todeliver DC to a load and including a linear transformer having a primarywinding and a secondary winding, control circuit means operative fromsource current to generate timed and shaped control pulses theamplitudes of which are substantially constant and the duration of whichare conformed in inverse magnitude to the instantaneous voltage of thesource; switching means actuated by said control pulses to apply sourcecurrent in successive power pulses to said primary winding whereby thelatter is energized by pulses of source current which have asubstantially constant energy content; means in said output circuitoperative to rectify and integrate power pulses derived from saidsecondary winding to provide a unidirectional and substantially steadystate current for utilization by a load, said transformer primarywinding being split into two sections and said switching means beingactuated in power cycles by gating pulses applied thereat in each powercycle, and said control circuit means includes an oscillator providingtwo timing pulses per cycle of oscillation, together with multivibratormeans triggered under control of both timing pulses in each oscillatorcycle to produce angularly spaced gating pulses in pairs in each powercycle with the spacing between the successive gating pulses in each pairbeing changed in inverse proportion to each change of source voltage atany given instant from said normal value thereof, said switching meansbeing operative under control of each pair of gating pulses in eachpower cycle to switch a power pulse of source current into a differentone of said primary sections, multiple arrays, each comprising aplurality of transistors having base, emitter and collector electrodes;said multiple arrays comprising a group operatively associated with eachtransformer primary section, and the several arrays comprising each saidgroup being connected in parallel and with the bases of the firsttransistor in each array of the group being connected to define a jointinput base terminal, driving circuits, said joint input base terminalconnecting with a corresponding driving circuit, and the respectivecommon collector terminals connected to define a joint coLlectorterminal; and the emitter electrodes of the last transistors in eacharray being connected to define a joint emitter terminal, and the saidjoint collector and emitter terminals being connected to source currentthrough the appertaining primary section.
 2. Apparatus according toclaim 1 wherein the windings comprising the primary sections and thesecondary of said transformer are of the bifilar type, andpulse-integrating means in the output circuit for presenting apredominantly inductive input to the rectified power pulses derived fromthe secondary winding as aforesaid.
 3. Apparatus according to claim 2further characterized by the provision of means for adjusting foroverdrive in one or the other of said transformer primary sections dueto difference in strength between the power pulses produced in companionhalf-cycles of any full power cycle, said adjusting means includingmeans selectively connectable with said control circuit means to modifythe respective control pulses during either half-cycle of any givenpower cycle, such that the weaker pulses of one half-cycle is widenedand the stronger pulse of the companion half-cycle is narrowed, eachrespectively by an amount proportioned with respect to the other toproduce substantially equal driving effects for the appertaining powerpulses respectively energizing said primary sections in the given powercycle.
 4. Apparatus according to claim 1 further characterized by theprovision therein of output voltage regulating means including a deviceresponsive to voltage in said output circuit and cooperative with saidcontrol circuit means responsive to changes in output voltage from apredetermined normal value thereof, to modify the duration of saidcontrol pulses in inverse magnitude to the voltage existing in saidoutput circuit from moment to moment, but substantially independently ofthe conforming action effected by said control circuit means responsiveto changes in source voltage, whereby to maintain said output voltagesubstantially at said normal value thereof.
 5. Apparatus according toclaim 1 further characterized by the provision of start-stop subcircuitmeans including further electron valve means and cooperative circuitmeans connecting with source current and said first subcircuit means foroperation to delay action of full source voltage when the convertercircuit is turned on for operation by said DC source until such time assaid first subcircuit means is fully operative in switching action asaforesaid; said start-stop subcircuit means being further operative tosupply power to continue said switching action a predetermined length oftime after said converter circuit is turned off to stop operationthereof by said DC source.
 6. Apparatus according to claim 21 whereinthe said conformation of parameters is such as to reduce the energycontent of said pulses to a predetermined low value during the start, atleast, of said switching action.
 7. A DC-to-DC converter including apower transformer having a secondary winding delivering converted DCenergy to an output circuit, and a primary winding energized by powerpulses of direct-current from a DC source having a predetermined normalvoltage; circuit means operative in cycles at a predetermined frequencyto convert source current into square-wave power pulses at saidfrequency; switching means operative responsive to gating pulses in setsincluding a first and a last gating pulse in each set to apply saidpower pulses in power cycles to said primary winding; means generatinggating pulses in sets as aforesaid and applying same to said switchingmeans in power cycles each including at least one set of gating pulses;the angular spacing between the first and last gating pulse of each saidset determining the width of each corresponding power pulse; and pulsewidth control means operative responsive to the magnitude of theexisting source voltage during any power cycle to position the lastgating pulse angularly relatiVe to the first such pulse in each setinitiating a power cycle to determine a normal pulse width correspondingto said normal source voltage, said pulse width control means beingfurther operative to change such position in an inverse proportion tothe deviation of said source voltage from said normal value from cycleto cycle and thereby adjust the pulse width as necessary from time totime to maintain a substantially constant energy level in said powerpulses notwithstanding variations in source voltage betweenpredetermined limits, at least.
 8. Apparatus according to claim 7wherein said pulse generating means includes timing means employingresistance and capacitance in an R/C timing combination the timeconstant of which is variable in accordance with the magnitude of acharging voltage acting therethrough, and said R/C combination isconnected to be charged by the voltage of said source whereby to alterthe angular relation between the first and last pulses of any set ofgating pulses to determine said normal and adjusted widths in the mannerand for the purpose aforesaid.
 9. In a DC-to-DC converter circuitadapted to be connected to a source of direct-current and turned on andoff in respect thereto to start and stop the converting action thereof,the combination with an output circuit adapted to deliver converted DCto a load; transistor means adapted to be turned on and off in switchingaction to energize said output circuit in power pulse of DC conductedthereto by said transistor means; timing circuit means operative toactuate the transistor means in switching action as aforesaid; andstart-stop guard means comprising a first subcircuit means operative toprevent action of full source voltage in said transistor means atstarting turn on of the converter circuit for a predetermined delayinterval; means cooperative with said timing circuit means to cause saidswitching action to be in full progress during said interval; andcircuit means operative to continue said switching action apredetermined time after the converter circuit is turned off to stop theconverting action.